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četvrtak, 28.5.2026 9:00 - 12:00, Liburna, Hotel Admiral, Opatija 9:00 - 10:15  Radovi   1. M. Matić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia), V. Sharma (Department of Mechanical and Materials Engineering, University of Turku, Finland, Turku, Finland), M. Poljak (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Electrical Modeling of Randomly Oriented Copper Nanowire Networks  Copper nanowire (CuNW) networks are promising candidates for flexible, transparent conductive surfaces and nanoelectronic interconnects due to their high intrinsic conductivity and compatibility with scalable fabrication methods. The electrical performance of CuNW networks is strongly influenced by network topology, nanowire geometry, and inter-nanowire junction properties. In this work, we present an efficient and scalable modeling framework for large CuNW networks with arbitrary patterns and apply it to study the sheet resistance of randomly oriented CuNW networks. Individual nanowires are described using physically accurate resistivity models that account for surface and grain-boundary effects, while inter-nanowire interactions are represented by resistive junctions. This approach is used to investigate computational limitations and the impact of leakage on sheet resistance in randomly oriented CuNW networks. The results show that up to an 8.6× speedup can be achieved by parallelization on 20 cores, but this comes at the cost of high RAM usage, up to 120 GB, which limits parallelization. Furthermore, due to leakage, sheet resistance is up to 1.7× higher than without leakage for structures with low mass density and low contact quality, while for higher mass density, its impact is lower, at the sub-1.2× level. 2. H. Aturi, R. Murthy (Alliance university, Bengaluru, India) Variability-Aware Jiles–Atherton and ML Modeling of 10 nm HZO Ferroelectric Capacitors for Integrated Electronics  Ferroelectric Hafnium zirconium oxide (HZO) is a promising platform for non-volatile memory and neuromorphic hardware. Still, its deployment in cryogenic and variability-aware applications requires accurate, physics-based compact models. This work presents a modeling framework for a 10 nm HZO ferroelectric capacitor implemented as 𝐀𝐮/𝐀𝐥𝟐𝐎𝟑/𝐇𝐙𝐎/𝐓𝐢𝐍 metal–insulator–ferroelectric–metal (MIFM) structure that emulates the gate stack of MFIS-type FeFETs. An adapted Jiles–Atherton (JA) hysteresis model is calibrated to experimental data and reproduces a remanent polarization 𝐏𝒓 approximately equals to 28 μC/cm2, and a coercive field 𝐄𝐜 approximately equals 2.5 MV/cm with the loop area and 𝐏𝐫 accuracy exceeding 94% over a 50–300 K temperature range, indicating suitability for both room-temperature and cryogenic operation. To address the computational bottleneck of variability-aware design, a machine-learning surrogate based on Lasso regression is introduced, achieving an 𝐑𝟐 of 0.9985 and a root-mean-square error (RMSE) of 0.0199, while delivering a 𝟏𝟎𝟓× speedup in inference time (454 μs/device) relative to iterative TCAD solvers. This acceleration enables efficient, rapid Monte Carlo yield analysis for large-scale (megabit) memory arrays. Finally, a parameter sensitivity analysis reveals the physical correlation between domain-wall dynamics and device performance, providing a roadmap for design–technology co-optimization (DTCO) and a pathway for future energy-efficient ferroelectric hardware. 3. T. Vukadin, E. Kramarić, M. Poljak (University of Zagreb Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Contact Resistance in One-Dimensional Si2Br4 GAA FETs with Edge Contacts from Quantum Transport Simulations  One-dimensional van der Waals material Si2Br4 is theoretically and numerically analyzed as a channel material for gate-all-around field-effect transistor (GAA FET) architecture. Wannierized Hamiltonians obtained from density functional theory (DFT) calculations are combined with the Green’s function formalism to investigate the contact resistance (RC) in Si2Br4 GAA FETs in terms of the broadening parameter, Fermi energy level, and nanowire length by employing two different approaches, i.e. extraction from the ON-state current and extraction from the conductance. The two methods show good agreement for a Fermi energy of 45 meV above the conduction band minimum. We report the minimum RC of 41.4 kΩ (193 Ωµm) for the optimum nanowire length of ≈15 nm. Simulations at cryogenic temperatures show rapid growth of RC at low temperatures, reaching 94.9 Ω (443 Ωµm) at 4.2 K, with the lowest contact resistance of 35.9 kΩ (168 Ωµm) occurring at 100 K. We find that the RC in Si2Br4 GAA FET is comparable to or lower than the values reported for graphene and phosphorene nanoribbon devices of similar size. 4. E. Hobbacher, F. Magerl (Chair of Electron Devices, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen, Germany), C. Pixius, J. Förthner, A. May, M. Rommel (Fraunhofer Institute for Integrated Systems and Device Technology IISB, Erlangen, Germany), J. Schulze (Chair of Electron Devices, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen, Germany) Low-Temperature Characterization of Sheet and Contact Resistance of 4H-SiC Test Structures from 300 K to 4 K  In harsh or cryogenic environments, the electrical behaviour of highly doped regions in 4H-SiC plays a key role in the performance of SiC-based electronic devices, yet remains insufficiently understood. This work investigates the temperature dependence of sheet resistance (Rsh) and specific contact resistivity (ρc) in highly doped n+ and p+ regions of a 4H-SiC CMOS technology. Electrical measurements are performed on Transmission Line Method (TLM) structures, Van der Pauw (VdP) geometries, meander resistors and contact chains in the temperature range from 300 K down to 4 K. In n+ regions, linear current–voltage characteristics are maintained over the full temperature range, enabling extraction of Rsh and ρc down to 4 K, with both parameters increasing moderately with decreasing temperature. In p+ regions, Rsh and ρc increase sharply with decreasing temperature, restricting extraction to minimum temperatures between 70 K and 140 K depending on the test structure. Below this range, incomplete dopant ionization and degraded ohmic contact behaviour result in non-linear characteristics. VdP structures provide stable determination of Rsh for both doping types. For ρc extraction, contact chains enable valid extraction down to the lowest temperatures in n+ regions, whereas in p+ regions TLM structures provide consistent values within the accessible temperature range. The observed trends are supported by calculations using temperature-dependent carrier statistics and mobility. 10:15 - 10:45  Pauza  10:45 - 12:00  Radovi  5. A. Tabaković, F. Bogdanović, L. Marković, T. Suligoj (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Interdependence of Mobility and Incomplete Ionization Models at Cryogenic Temperatures in Si BJTs  This work presents a comprehensive cryogenic modeling approach for Si BJTs, based on the measured characteristics of a Horizontal Current Bipolar Transistor (HCBT), with particular emphasis on incomplete ionization and carrier mobility as the dominant current-determining mechanisms. A systematic refinement of the dopant activation energy formulation, combined with the implementation of the Philips Unified mobility model, enables accurate reproduction of measured collector and base currents across a broad temperature range (300 K–40 K). The study demonstrates that the temperature-dependent term in the activation energy must contribute more when the Philips Unified mobility model is included, because incomplete ionization in the intrinsic base region dominates low-temperature behavior. On the other hand, varying the hole mobility in the emitter primarily impacts base current characteristics, and is determined to be 1.75·104 cm2/Vs at 40 K for optimal fitting. The proposed physics-based parameter optimization strategy ensures reliable separation of scattering mechanisms and enhances the predictive accuracy of transistor performance modeling under cryogenic conditions. 6. D. Novaković, M. Marušić, I. Berdalović, T. Suligoj (Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia) Impact of Traps on the Threshold Voltage Shift in Novel Buffer-Free GaN HEMTs  This paper investigates the dependence of the threshold voltage shift in buffer-free GaN high electron mobility transistors (HEMTs) on trapping phenomena occurring at different spatial locations within the device structure. Structures with two different undoped GaN channel thicknesses are analyzed in order to explain experimentally observed variations in threshold voltage. In the first part of the study, trapping at the back interface between the GaN channel and the AlN nucleation layer is investigated. Hydrodynamic simulations are employed to analyze the distribution of hot electrons and their interaction with acceptor traps at the interface. Three different trap models are considered, each capable of reproducing the experimentally observed dependence of threshold voltage on the channel thickness to a certain extent. In the second part of the work, traps located beneath the gate are analyzed, including both bulk and interface traps at different positions within the epitaxial stack. The results indicate that realistic trap concentrations have a significant impact on the device characteristics only if they are located in close proximity to the GaN channel. These findings highlight the importance of trap location in determining the threshold voltage behavior of not only buffer-free GaN HEMTs, but GaN-based HEMTs in general. 7. L. Marković (Micro and Nano Electronics Laboratory, Faculty of Electrical Engineering and Computing, University o, Zagreb, Croatia), T. Knežević (Division of Materials Physics, Ruđer Bošković Institute, Zagreb, Croatia), K. Azizur-Rahman (Center for Integrated Nanotechnologies, Sandia National Laboratories, Albuquerque, United States), J. Mah (School of Computing and Augmented Intelligence, Arizona State University, Tempe, United States), L. Nanver, A. Attariabad (MESA+ Institute, University of Twente, Enschede, Netherlands), K. Wang (Department of Electrical and Computer Engineering, University of California Los Angeles, Los Angeles, United States), T. Suligoj (Micro and Nano Electronics Laboratory, Faculty of Electrical Engineering and Computing, University o, Zagreb, Croatia) FTIR-Based Broadband Characterization of NIR Ge-on-Si Photodiodes Using Source Spectrum Reconstruction  Broadband photodetectors require characterization techniques capable of resolving wide spectral ranges with high resolution. Conventional approaches rely on monochromator or tunable-laser systems, which require sequential wavelength scanning and complex optical setups. In this work, Fourier-transform infrared (FTIR) spectroscopy is used to rapidly acquire a high-resolution, continuous optical spectrum of a Ge-on-Si photodetector with a cutoff wavelength of ~1560 nm. A previously reported calibration procedure, adapted for the present experimental setup, is applied to reconstruct the power spectral density of the incident light using only the integrated pyroelectric reference detector of a commercial FTIR spectrometer. The impact of the correction is evaluated for different spectral bandwidths used in the calibration procedure, showing that calibration may be unnecessary for narrow-band spectral acquisition. The corrected Ge-on-Si spectrum is validated using monochromatic measurements at 670, 1310, and 1550 nm, as well as TCAD optical simulations. Satisfactory agreement above 1100 nm confirms the applicability of FTIR spectroscopy for rapid characterization of NIR photodetectors. 8. P. Bartulović, B. Požar, I. Berdalović, T. Suligoj (Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia) On the Lateral Distribution of Photoresponse in High-Voltage CMOS SPADs Below and Above the Breakdown Voltage  Novel structures of single-photon avalanche diodes (SPADs) fabricated in a commercial 180 nm high-voltage (HV) bipolar-CMOS-DMOS (BCD) technology have been characterized using a laser beam focused down to a full-width half-maximum (FWHM) spot size of 1.2 μm at a wavelength of 520 nm. The devices are biased near or above their breakdown voltage, and the impact of beam spot size and detector gain on the lateral distributions of photocurrent and photon detection probability (PDP) is analyzed, respectively. Significant differences in the photocurrent distributions are observed depending on the type and size of the avalanche multiplication region with respect to the metal opening defining the photoactive area, mainly attributed to light reflection from the metal edge. A difference of more than a factor of 2 in beam spot size in the silicon active region compared with the metal is also noted. On the other hand, the PDP, peaking at 22.3% at an excess voltage of 20 V above breakdown, shows a more uniform distribution over the active area compared with the photocurrent distribution below breakdown on the same device. The study serves as a general guideline for characterizing the position-dependent photoresponse of solid-state photodetectors with internal amplification, taking into account on-chip isolation layers and metal shielding around the active region. četvrtak, 28.5.2026 15:00 - 19:00, Liburna, Hotel Admiral, Opatija 15:00 - 16:45  Radovi  1. A. Žamboki, L. Gočan (University of Zagreb, Faculty of electrical engineering, Zagreb, Croatia), J. Mikulić, G. Schatzberger, J. Fellner (ams-OSRAM AG, Premstaetten, Austria), T. Mandić, A. Barić (University of Zagreb, Faculty of electrical engineering, Zagreb, Croatia) Stress Analysis and Measurement of CMOS Reference Current Sources  This paper presents a mathematical analysis and measurements of the effects of stress on CMOS reference current sources. Currently, there is a lack of comprehensive analysis regarding the impact of stress on reference current sources. This makes it difficult to design current references with reduced sensitivity to mechanical stress and to implement stress-compensating methods. This paper provides a detailed, stress-oriented mathematical analysis of CMOS current sources, yielding a reference current versus stress formula for various circuit layout topologies. Mechanical stress measurements of different current source topologies confirm the mathematical analysis and demonstrate the impact of the rotation of individual circuit elements in the layout on stress response. Stress measurements also confirm the previously developed methodology for reducing mechanical stress sensitivity of circuits through component rotation in layout. 2. L. Gočan, A. Žamboki (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia), J. Mikulić, G. Schatzberger, J. Fellner (ams-OSRAM AG, Premstaetten, Austria), T. Mandić, A. Barić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Stress Distribution in Packaged Chips and on Bare Silicon Stripes  This paper compares the mechanical stress distribution in packaged chips and on bare silicon stripes. The stress distribution is extracted using an 8-by-8 array of mechanical stress sensor cells. Each cell comprises four Wheatstone bridge stress sensors: two pMOS sensors of different sizes and two nMOS sensors of different sizes. The paper focuses on the in-plane normal stress difference measured with the pMOS Wheatstone bridges. The measurement results are consistent across 19 samples of the packaged chips and 20 samples of the silicon stripes. The chips are packaged in a J-leaded ceramic chip carrier, and the measurements indicate a stress distribution caused by the adhesive used in the die attach process. The sensor array is also placed at the centre of the silicon stripes. Measurements without externally applied stress show increased stress levels near the pad ring. Analysis of the stress distribution enables the implementation of appropriate stress compensation steps in the design. 3. T. Katavić, I. Budić, T. Marković (University of Zagreb Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Design of a Class AB Operational Amplifier for Current Signals in the Frequency Range up to 100 kHz  This paper presents the design and implementation of an amplifier optimized for reliable operation with output current signals up to 100 kHz. The design is based on a custom operational amplifier, implemented in 180-nm CMOS technology. The designed amplifier forms the core of an improved Howland current source with resonated inductive loads having 1 ohm to 10 ohms series resistance. The operational amplifier supports rail-to-rail input and output operation. The amplifier achieves a gain-bandwidth product (GBW) of more than 13 MHz with a DC open-loop gain higher than 120 dB, with phase margin exceeding 60 degrees. In an improved Howland topology, the amplifier consistently delivers sinusoidal currents of more than 50 mA peak-to-peak up to 100 kHz and across the full load range. 4. I. Budić, T. Marković (University of Zagreb Faculty of Electrical Engineering and Computing, Zagreb, Croatia) High-Accuracy System for Sensing Sinusoidal Current Signal Amplitude in the Frequency Range from 1 Hz to 100 kHz  A sinusoidal current signal amplitude sensing system designed for operation in the frequency range from 1 Hz to 100 kHz is presented. The proposed system comprises an integrated 12-bit analog-to-digital converter and a multi-stage amplifier based on low-offset voltage operational amplifiers in feedback topologies. It is developed as part of a larger electronic system for neuromodulation applications, where the amplitude of the generated sinusoidal current signal must be continuously monitored with high accuracy. The topology of the sinusoidal current amplitude sensing system is explained theoretically and tested using simulation software. A printed circuit board is designed for the electronic circuit. The developed electronic system is characterized by measurements. The sinusoidal current amplitude sensing system achieves high accuracy over the entire frequency range of interest, with a relative current amplitude sensing error lower than ±1.3%, which is particularly important for the application. The user receives information about the sensed current amplitude via the user interface. The maximum amplitude of the sensed sinusoidal current signal for which the system is designed, over the frequency range from 1 Hz to 100 kHz, exceeds 1 A peak-to-peak, as required for the application. 5. M. Križan, I. Budić, T. Marković (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Design of a Scalable Synchronized Multi-Channel Sinusoidal Voltage Signal Source for Neuromodulation in the Frequency Range from 1 Hz to 500 kHz  The synchronized multi-channel voltage signal source for operation in the frequency range from 1 Hz to 500 kHz is designed. A key characteristic of the multichannel voltage source is scalability to drive an arbitrarily large array of amplifiers that supply current to specially designed coils, while maintaining a low phase error and high spectral purity of all the generated voltage signals. The proposed system is controlled via the Serial Peripheral Interface (SPI) and consists of a clock generator circuit built around a commercially available clock buffer chip, an output signal synchronization circuit built around the integrated waveform generator AD9959, and an output stage with additional AD9959 generators. The multi-channel system topology is scalable to 64 output signals. The system spectral purity and phase error are measured in the frequency range of interest. 6. D. Vinko, J. Spišić, L. Filipović, D. Bilandžija (Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, Croatia) Fresh Water Battery for Ultra-Low-Power Applications  This paper presents a functional concept for a fresh water battery capable of powering ultra-low-power devices. The fresh water battery is constructed with copper (Cu) and zinc (Zn) electrodes, using fresh water as the electrolyte. The current-voltage characteristics of the proposed fresh water battery are analysed, measured, and evaluated. Testing included various configurations of Cu and Zn electrodes with both tap water and different brands of bottled water. Based on the available output voltage, current, and power levels of the fresh water battery, two supplemental electronic circuits were developed. A DC-DC converter was designed to boost the low output voltage of the fresh water battery from approximately 0.7 V to voltage levels exceeding 6 V at idle. The second supplemental circuit is an energy management circuit, developed to support load devices with higher current demand. Both circuits were designed with strict limitations on current consumption, due to the low current drivability of the fresh water battery (in the range of a few hundred μA). Measurements on the fabricated prototype device show that both supplemental circuits achieved ultra-low current consumption, with 15 μA for the DC-DC converter and 800 nA for the energy management circuit. 16:45 - 17:15  Pauza  17:15 - 18:45  Radovi  7. M. Štefanac, M. Pavlek, D. Babić (Eridan Communications d.o.o., Zagreb, Croatia) Emissivity-Free Thermal Imaging of GaN/SiC Radiofrequency Circuits  Detailed studies of local heating on electronicchip surfaces require temperature imaging calibrated to eliminate the effect of surface emissivity variations. This study presents an approach using a commercially available infrared camera, pre-calibrated for a single emissivity. Infrared emission images are acquired at a sequence of temperatures spanning the device’s operating range, forming a data cube where each pixel has a corresponding look-up table. The full die surface temperature is then obtained by interpolating these tables. This method does not require knowledge of the surface emissivity and does not rely on proprietary camera calibration data, which are often publicly unavailable. 8. M. Milanović, H. Džapo (Faculty of Electrical Engineering and Computing, Zagreb, Croatia) A Phonocardiography System for Heart Rate and Cardiorespiratory Monitoring Using Acoustic Signal Processing  Monitoring cardiac activity using non-invasive low-cost sensing technologies is gaining increasing attention for continuous and unobtrusive health monitoring. Phonocardiography (PCG) records heart sounds generated by the mechanical activity of the heart and provides complementary information to electrical and optical sensing techniques. This paper presents a functional prototype of a low-cost microphone-based system for heart activity monitoring. The system combines an STM32F407 microcontroller, an ICS-40180 analog MEMS microphone, and a dedicated signal processing algorithm for robust detection of the first (S1) and second (S2) heart sounds. A fully PCG-based segmentation and heart sounds classification algorithm based on systolic duration and inter-sound timing relationships is proposed. The algorithm was evaluated on 17.5 minutes of laboratory-recorded data comprising approximately 1,500 cardiac cycles. Sensitivity and specificity of approximately 95% and 97% were achieved for both S1 and S2 detection. Heart rate estimation yielded a mean absolute error of about 1 bpm. Additionally, extracted temporal and morphological features indicate potential for heart rate variability analysis, respiratory monitoring, and blood pressure estimation. 9. Z. Šverko, S. Vlahinić, M. Vrankić, N. Stojković (University of Rijeka Faculty of Engineering, Rijeka, Croatia) Exploring Directed Functional Connectivity in EEG Using Granger Causality: Potential Insights into Frontotemporal Dementia  Understanding the dynamics of brain networks is essential for exploring neurodegenerative processes. This study investigates the potential of Directed Functional Connectivity (DFC) analysis using Granger Causality (GC) applied to EEG signals from individuals diagnosed with Frontotemporal Dementia (FTD) and cognitively healthy controls. Granger Causality provides a statistical framework for estimating directional interactions between neural regions, allowing examination of the flow of information within brain networks. EEG recordings were preprocessed to remove artifacts, followed by computation of GC values between key cortical regions across relevant frequency bands. The study explores the possibility that directed connectivity analysis may reveal differences in neural network organization between FTD patients and healthy participants. By analyzing the directionality of interactions, this approach offers a framework for better understanding functional network dynamics and alterations associated with neurodegenerative conditions. The use of GC-based metrics complements traditional EEG analyses and provides a method to investigate neural communication patterns in both healthy and pathological states. Overall, this work highlights the applicability of directed connectivity approaches in EEG research and their potential to advance knowledge of brain network organization in neurodegeneration, without making assumptions about diagnostic outcomes. 10. H. Mihaldinec (Ultrax Technologies d.o.o, Mače, Croatia), H. Džapo (Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia) Simulation-Based Assessment of UWB Anchor Auto-Calibration Solvers for GNSS-Denied Emergency Response  Effective localization of firefighters in GNSS-denied environments is critical for safety and operational efficiency. While Ultra-Wideband (UWB) technology offers high-precision ranging, traditional setups rely on pre-surveyed static anchor networks, which are impractical for rapid emergency deployment. This paper proposes an incremental, ad-hoc anchor deployment strategy where a network extends from a minimal external reference frame into a structure using mobile nodes. We formulate the calibration of this extending network as a fundamental geometric problem and present a comparative simulation study of four auto-calibration algorithms: Linear Least Squares (LLS), Cayley-Menger Determinant (CMD), Closed-Form Position (CFP) estimation, and Analytical Intersection. We evaluate these methods within a discrete-event simulation environment that models clock skew and jitter. Our results indicate that Linear Least Squares (LLS) achieves the most robust performance, delivering the lowest calibration and localization error under realistic timing jitter conditions 11. Z. Mandić, T. Begović, S. Lubura (University of East Sarajevo, Faculty of Electrical Engineering, East Sarajevo, Bosnia and Herzegovina) Frequency-locked Loop With Kalman-based OSG Immune To The DC-Offset  A frequency-locked loop synchronization with an inherent orthogonal signal generator is one of the key enablers of reliable synchronization for grid-connected power converters. An accurate and robust grid synchronization is essential for stable control and power regulation in those applications. Conventional structures, commonly based on second-order generalized integrators, may operate irregularly in the presence of measurement noise, harmonic distortion, frequency changes and a DC-offset component. To address this issue, a modified Kalman-based generator with the DC-offset immunity is integrated into the conventional frequency-locked loop. The proposed approach utilizes a state-space oscillator model equipped with an additional state for DC-offset component estimation, enabling generation of orthogonal signal with DC-offset rejection. The effectiveness of the proposed loop is verified in the MATLAB/Simulink environment under numerous tests such as DC-offset introduction, sudden amplitude and frequency changes. The shown results demonstrate accurate grid voltage estimation and ripple-free frequency estimation with providing robustness and accuracy against conventional structures.

Basic information:

Marko Koričić (Croatia), Vladimir Čeperić (Croatia), Mirko Poljak (Croatia), Tomislav Markovic (Croatia)

Slavko Amon (Slovenia), Dubravko Babić (Croatia), Željko Butković (Croatia), Maurizio Ferrari (Italy), Mile Ivanda (Croatia), Branimir Pejčinović (United States), Jörg Schulze (Germany), Tomislav Suligoj (Croatia), Aleksandar Szabo (Croatia)

Juncheng Bao (China), Milan Bjelica (Serbia), Vladimir Čeperić (Croatia), Tihomir Knežević (Croatia), Marko Koričić (Croatia), Mindaugas Lukosius (Germany), Tvrtko Mandić (Croatia), Tomislav Marković (Croatia), Bart Nauwelaers (Belgium), Mirko Poljak (Croatia), Davor Vinko (Croatia)

The student discount doesn't apply to PhD students.

NOTE FOR AUTHORS: In order to have your paper published, it is required that you pay at least one registration fee for each paper. Authors of 2 or more papers are entitled to a 10% discount.
 

Marko Koricic
University of Zagreb
Faculty of Electrical Engineering and Computing
Unska 3
HR-10000 Zagreb, Croatia

Phone: +385 1 6129 953
GSM: +385 98 671 391
Fax: +385 1 6129 653
E-mail: marko.koricic@fer.hr

The best papers will get a special award.
Accepted papers will be published in the ISSN registered conference proceedings. Papers presented at the conference will be submitted for inclusion in the IEEE Xplore Digital Library. 

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