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Hibridni događaj
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| Radovi |
M. Bendra, S. Fiorentini, J. Ender, R. Orio, T. Hadamek, N. Jorstad, B. Pruckner, S. Selberherr (Institute for Microelectronics TU Wien, Vienna, Austria), W. Goes (Silvaco Europe Ltd., Cambridge, United Kingdom), V. Sverdlov (Institute for Microelectronics TU Wien, Vienna, Austria)
Back-Hopping in Ultra-Scaled MRAM Cells 
The development of advanced magnetic tunnel junctions with a footprint in the single-digit nanometer range can be achieved using an elongated multilayer ferromagnetic free layer structure. Using the spin drift-diffusion model, we investigated the back-hopping effect in ultra-scaled STTMRAM devices. Unwanted switching of the middle-layer structure has been identified as a possible cause of the back-hopping effect, which leads to a writing error in the magnetization state of the free layers. To understand the switching of the free layer, the torque acting on both parts of the composite free layer is studied in detail. A reduction in the size of MRAM components to increase the memory density leads to lower anisotropies and thus increases the likelihood of back-hopping due to the presented mechanism. A possible solution to avoid erroneous switching is to increase the magnetic anisotropy of the layers.
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I. Prevarić, M. Matić, M. Poljak (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Tunneling Attenuation and Leakage Current in MoS2 Nanoribbon MOSFETs
We study the OFF-state leakage current in quasi-one-dimensional MoS2 nanoribbon (MoS2NR) FETs using ab initio Hamiltonians and quantum transport simulations based on Green’s functions. Complex band structure is computed for these devices and the energy-dependent tunneling attenuation inside the bandgap is obtained. We investigate the tunneling component of the OFF-state leakage for sub-20 nm long and sub-3 nm wide MoS2NR FETs, using the under-the-barrier (UTB) and top-of-the-barrier (ToB) ballistic models. We report that using the parabolically-approximated attenuation overestimates the OFF-state leakage significantly. Furthermore, we demonstrate that all MoS2NR FETs show good tunneling suppression due to high attenuation even for the shortest devices where the OFF-state leakage is under 16.5 nA/μm for nFETs and lower than 22 nA/μm for pFETs.
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M. Matić, M. Poljak (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Transport Properties and Device Performance of Quasi-One-Dimensional MoS2 FETs
We investigated the bandstructure, transport and device properties of semiconducting MoS2 nanoribbons (MoS2NR) with hybrid OH-passivated armchair edges using orbitally-resolved ab initio Hamiltonians and quantum transport simulations based on Green’s functions. The impact of MoS2NR width scaling on the bandstructure, transmission, bandgap, injection velocity, charge density and ON-state current are analyzed in detail using the ballistic FET model. We find that sub-3 nm-wide and ~15 nm-long MoS2NR FETs offer low driving currents under 0.43 mA/μm for nFETs and under 0.6 mA/μm for pFETs. Moreover, the current is only weakly modulated by nanoribbon width downscaling due to immunity of the MoS2NR bandstructure to quantum confinement effects.
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M. Poljak, M. Matić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Bandgap Narrowing in Silicene Nanoribbons with Metal Edge Contacts
By employing atomistic quantum transport simulations we investigate the impact of metal edge contacts on the transport gap (ETG) of silicene nanoribbons (SiNR). Transmission and ETG are investigated for sub-5 nm-wide and sub-15 nm-long SiNRs for various metal-device interaction strengths. We find that metallization occurs in certain cases, especially in wider and shorter devices, which sets fundamental limits to device scaling of potential SiNR-based field effect transistors (FET). The findings are elaborated through analytical and numerical examples by discussing transmission and eigenvalue evolution with increasing metal-device interaction.
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K. Japec, M. Matić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia), R. Lukose, Germany), M. Lisker, Germany), M. Lukosius (IHP - Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), Germany), M. Poljak (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Determining Graphene and Substrate Quality from the Coupled Hall Mobility Measurements and Theoretical Modeling
An increase of mobility up to ~2600 cm2/Vs is observed in graphene by Hall bar characterization within the temperature range from 40 K to 300 K. The increasing trend is attributed to Coulomb scattering by employing theoretical modeling based on the momentum relaxation time approximation of the Boltzmann transport equation. We also find that at room temperature and for higher charge densities additional mechanisms such as lattice defect and/or substrate corrugation scattering become important and restrict the mobility down to only ~200 cm2/Vs and carrier mean free paths well under ~35 nm.
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| Pauza |
| Radovi |
A. Žamboki, L. Gočan (Faculty of Electrical Engineering and Computing, Zagreb, Croatia), J. Mikulić, N. Bako, G. Schatzberger (ams-osram AG, Premstaetten, Austria), T. Marković, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Stress-dependent MOSFET Model for Use in Circuit Simulations
This paper presents a stress-dependent MOSFET model based on existing transistor models. The encapsulation of chips is often made from polymers (such as epoxy) which are poured over the silicon chips. When the encapsulation cools, it generates a significant amount of static mechanical stress in the ICs which changes their performance. To compensate for the offsets caused by the stress, chip designers need to be able to simulate the effects of stress on their circuits and design stress sensors and active stress-compensating circuits. In this paper, a stress-dependent MOSFET model is implemented by combining existing transistor models and a Verilog-A cell. In this way, temperature, corner and other transistor variations can be simulated in combination with stress. Simulations show that this model can be used to simulate the stress effects on circuits and to design and optimize stress-compensating circuits.
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L. Gočan, A. Žamboki (Faculty of Electrical Engineering and Computing, Zagreb, Croatia), N. Bako, J. Mikulić, G. Schatzberger (ams-osram AG, Premstaetten, Austria), T. Marković, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Low-Power Frequency-Locked Loop Circuit with Static Frequency Offset Cancellation
A phase-locked loop (PLL) is an important and commonly used electronic circuit in various electronic systems. Its main drawback is the use of an RC low-pass filter which takes up the majority of the PLL area on the chip. The RC low-pass filter is necessary to ensure the PLL stability. To mitigate this issue, a frequency-locked loop (FLL) is used because the stability of an FLL system depends on the Miller capacitance inside of the operational amplifier, which drastically reduces the capacitor size and thus the chip area. This paper presents an improved design of a fully integrated FLL. It is based on a single frequency-to-voltage converter (FVC) which uses a single capacitor and a single charging current for the frequency-to-voltage conversion of both the input and output frequencies. The use of one FVC reduces the static frequency offset caused by the mismatch between the FVCs. The circuit is implemented in a 180-nm CMOS process. The measurements show that the new FLL design has increased precision and accuracy and similar chip area compared to the previous design. It has higher power consumption, increased delay time, overshoot and settling time, but they are comparable to those of the previous design.
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M. Kovac, M. Potocny, D. Arbet, R. Ondica, R. Ravasz, V. Stopjakova (Slovak University of Technology in Bratislava, Bratislava, Slovakia)
Low-Power CMOS Frequency Comparator
The paper is focused on the design and analysis of a fully on-chip integrated frequency comparator (FC) implemented in 65 nm CMOS technology. The proposed FC employs digital pre-processing stage followed by low-power input and output rail-to-rail voltage comparator to ensure accuracy of evaluation of input frequencies up to 1 MHz with supply voltage of 1.2V and power consumption in units of μW. The FC accepts signals with independent duty cycles and delays without necessity of any correlation between signals to confirm block universality. Presented results obtained by simulations shows robustness of proposed topology over process, temperature and supply voltage variations. The presented FC has been used in complex ultra-low power systems.
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I. Franković, F. Mikić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia), J. Mikulić, N. Bako, G. Schatzberger (ams-osram AG, Premstaetten, Austria), A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Measurement System for Characterization of a Resistor Array in 180-nm CMOS Technology
Integrated circuits are very sensitive to variations of temperature. All components used in IC design (transistors, resistors, capacitors and other components) are characterized with respect to the change of temperature by defining the temperature coefficients, usually of the first and second order. The temperature coefficient is usually specified as a fixed number for a given type of a resistor, i.e. it is assumed that the temperature coefficient does not depend on the dimension L (length) and W (width) of the resistor, which is usually not the case. This paper describes the system for characterization of the temperature coefficients of resistors having various lengths, widths and number of fingers, as well as different resistor types. The system is based on an array of resistors having 20 rows and 10 columns, which is sufficient to characterize 200 resistors. Each resistor cell can be selected separately, i.e. only one cell is active during the measurement. The measurement is based on 4-wire method, i.e. on forcing the current and measuring the voltage on the resistor. Digital circuits and analogue switches are built into the integrated circuit to enable the selection of each resistor cell.
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A. Traživuk, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Performance Analysis of 1-MHz Voltage-Controlled Ring Oscillator Designed in 180-nm CMOS Technology for Phase-Locked Loop
This paper presents a voltage-controlled ring oscillator designed and implemented in 180-nm CMOS technology to be used in a phase-locked loop. The performance of the circuit as a function of the temperature and supply voltage is measured. The measurements of the voltage-controlled oscillator are compared with the postlayout simulations.
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J. Zidar (Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, Croatia), I. Aleksi (Faculty of Electrical Engineering, Computer Science and Information Technology Osijek , Osijek, Croatia), T. Matić (Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, Croatia)
Analysis of Energy Consumption for SPI and I2C Communications in Ultra-low Power Embedded Systems
Utilizing components, algorithms, and communication protocols that satisfy low-power requirements is essential for the creation of ultra-low power devices. For environmental condition monitoring in the supply chain, products from the distributor to the consumer can travel for extended periods. Additionally, environmental conditions can be harsh, i.e., with temperatures below $0^{\circ}C$ that result in the decrease of battery charge. Therefore, to monitor package environmental conditions, it is necessary to lower the power consumption of all parts of the used embedded system. This paper analyzes the power consumption for SPI and I2C communication protocols, which are predominantly used for sensor communication in low-power embedded systems. Based on the results, we give considerations when using SPI/I2C protocol for developing ultra-low power embedded systems.
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| Radovi |
D. Bilandžija, D. Vinko, L. Filipović (Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, Croatia)
Genetic Algorithm Based Optimization of Circular Planar Coil Geometry with Homogenous Magnetic Field Distribution
A prominent problem in planar resonant wireless power transfer systems is significant efficiency decrease due to position misalignment of the receiver coil relative to postion of the transmitter coil. In order to keep stable efficiency even in such misaligned condition it is necessary to design transmiter coil which generate homogeneous magnetic field in charging plane. In this paper, a geometry of planar transmitter coil which consist of multiple concentric circles is optimized by utilizing evolutionary algorithms. Optimization goals are achieving as large as possible homogeneous region, i.e. portion of charging plane which is characterized by homogeneous magnetic field and as high as possible average value of magnetic field intensity within homogeneous region. Magnetic field evaluations are done by FEMM software. Optimized coil and its homogenous region is compared to the state-of-the-art.
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H. Štimac, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Analysis of the Effect of Differential-Mode and Common-Mode Impedance Matching on the Common-Mode Rejection Ratio of a Differential Electro-Optical Voltage Probe
A differential electro-optical voltage probe is characterized. The two main parts of the probe circuit are the attenuator circuit and the laser diode. The probe circuit is characterized by measuring S-parameters. The probe circuit has a stable common-mode rejection ratio (CMRR) up to 4 GHz, with a quick drop at higher frequencies. The probe circuit performance is simulated by combining the individual attenuator and laser characteristics connected in cascade. The differential-mode and common-mode signal propagation is analyzed in terms of voltage and impedance matching. The impedance matching between the attenuator and the laser, in combination with their individual characteristics, determines the CMRR frequency characteristic of the probe circuit. By suppressing the common-mode signal propagation, relative to the differential-mode signal, an electro-optical system with a CMRR higher than the nominal CMRR of the laser diode can be designed.
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C. Cetin, M. Magerl, C. Stockreiter (ams-OSRAM AG, Premstätten, Austria)
Measurement Setup for Characterizing Immunity of Integrated Circuits to Pulsed Electric Fields Using the IC stripline
A measurement setup is presented for characterizing the immunity of an ambient light sensor (ALS) integrated circuit (IC) to pulsed electric fields for consumer electronics products. The charge transferred to the photodiode during the rising and falling edges of the pulses is integrated and processed by the sensor, and it generates a shift in the ALS reading mean value. The pulsed electric fields up to 50 kV/m are applied to the IC using an open-terminated IC stripline with a septum height of 1.5 mm above the IC that is driven by voltage pulses with positive and negative amplitudes up to 80 V. The circuit for generating the voltage pulses synchronized with the on-chip photodiode integration phase is presented, and the achieved rising and falling edge characteristics are measured. The ALS reading shift is measured as a function of the voltage pulse amplitude, DUT orientation, level of illumination, and integrator gain. The relationship between the ALS reading shift and the electric field amplitude is established as a figure-of-merit for the immunity of the IC to pulsed electric fields.
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A. Križanić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia), R. Blečić, A. Broznić (Rimac Technology d.o.o., Sveta Nedelja, Croatia), A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Characterization of Ground Bounce and Conducted Emissions of Integrated Isolated DC-DC Converter
Isolation is used in automotive industry for safety reasons to galvanically isolate different domains. Isolated DC-DC converters are used to provide power across the isolation boundary. Integrated isolated power converters provide simpler, smaller, and more robust solutions compared to discrete solutions such as push-pull converters. Integrated isolated DC-DC converters operate at switching frequencies in the range of tens of MHz which makes them potential sources of electromagnetic emissions. Ground bounce is the main cause of the electromagnetic emissions. A 5V-to-5V integrated isolated DC-DC converter based on ISOW774x with interlayer stitching capacitance is developed on a printed circuit board. The ground bounce is characterized by time-domain measurements. The conducted emissions of the converter are measured according to CISPR25 standard. EMI filtering design for the converter is discussed.
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I. Krois, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Characterization of Class-E Resonant Converter Operating in MHz-Range
A class-E resonant converter operating at 2 MHz is designed and characterized. The values of the inductive and capacitive components used in the designed converter are calculated using a set of mathematical equations. Time-domain measurements are performed to analyze the steady-state operation of the designed converter and to verify an impact of the converter parameters on the zero-voltage-switching behavior. An impact of switching frequency on output voltage and impact of dutycycle on zerovoltage-switching effect is analyzed. Finally, conducted electromagnetic emissions of the converter are measured at the nominal operating point.
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K. Šolaja (Faculty of Electrical Engineering and Computing, Zagreb, Croatia), R. Blečić, A. Broznić (Rimac Technology d.o.o., Sveta Nedelja, Croatia), A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Design and Characterization of the Output Network of a High-Current Buck Converter
A 10-A automotive buck converter is designed and realized on a four layer printed circuit board. The output network is designed in the electromagnetic solver to account for the trace and package parasitic elements. The output network of the converter is simulated in the SPICE solver. The converter is characterized in the time domain by the load transient measurements and in the frequency domain by the shunt measurement method. Three configurations of the output network are compared. The results in the frequency domain and the results of the SPICE simulations are correlated.
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J. Baća (Faculty of Electrical Engineering and Computing, Zagreb, Croatia), R. Blečić, A. Broznić (Rimac Technology d.o.o., Zagreb, Croatia), A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Developing a Model of Buck Converter for EMI Filter Optimization by Circuit Simulations
Switching DC-DC converters for automotive applications typically require an input EMI filter to comply with the regulations. EMI filter for a 5-A automotive buck converter is designed in the frequency domain. To validate the performance of the filter the buck converter is modelled in the circuit simulator. The model consists of the power stage and the voltage-mode control loop. Discrete components are modelled by real models with parasitic elements. Performance of the converter with and without the filter is compared. Performance of the filter in the frequency and time domain is correlated. Circuit model of the complete converter allows to optimize the EMI filter prior to having the hardware.
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J. Kundrata, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Implementation of Voltage Regulation in a Spread-Spectrum-Clocked Buck Converter
Buck converters use spread-spectrum technique to reduce the electromagnetic emissions by distributing the electromagnetic interference in a frequency band around the switching frequency which consequently reduces the amplitude of the interference. Changing the switching frequency also changes the output voltage and causes an unwanted output voltage ripple. The output voltage ripple is then reduced by properly controlling the time delay used in the duty cycle controller of the buck converter. This paper presents a digital implementation of the duty cycle controller used in the buck converter which uses a phase-locked loop to generate the switching frequency. Changing the divider value of the phase-locked loop changes its output frequency, but this frequency change is not instantaneous and it is modeled as a second-order system response. The implementation of the duty cycle controller presented and analyzed in this paper aims to compensate for this transient change of the output frequency, i.e. the switching frequency and keep the duty cycle of the buck converter constant. The paper focuses on the compensation algorithm used to generate a constant duty cycle, as well as on the challenges of its digital implementation.
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A. Hećimović, L. Patrlj, V. Šunde, Ž. Ban (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Uninterruptible Power Supply System for Railway Infrastructure with Power Factor Correction and Immunity to Energy Strikes
This article discusses an uninterruptible power supply (UPS) for infrastructure devices used within the railway system. The main feature of this UPS is the high power factor and resistance to overvoltages that occur in the railway network. The aforementioned overvoltages occur when the train passes by the traction power substation (TPSS) and include multiple higher harmonics and other disturbances. High power factor correction (PFC) is obtained by adding a boost DC converter. Resistance to overvoltages is acquired using protective elements, i.e. varistors and inductors, as well as an additional overvoltage recognition device in the power supply network. Based on the sensor’s output, the part of the topology responsible for power factor correction can be turned off. PFC control is analyzed and optimized using MATLAB, and is later transferred over to PLECS, where converter’s components were connected together and simulated. The final results are presented in a form of comparative analysis of simulation results with and without the input protection as well as the analysis of the PFC’s efficiency.
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V. Zeleničić, M. Miletić, K. Raič Raguž, D. Sumina, I. Erceg (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Reduction of Current Harmonics in Data Center Power System Using Single-Phase Shunt Active Power Filter
With the significant increase of nonlinear loads in data center power systems, the losses due to the injection of current harmonics have also increased significantly. In order to reduce current harmonics, the use of active filters has become widespread. These filters use active components such as IGBT or MOSFET as well as R, L and C components. The power stage of the active filter consists of a voltage source inverter (VSI) and an LCL filter, which is used to filter the switching frequency. The control loop consists of a current controller and a PWM. In this paper, the results of two active filter simulations are compared. The first simulation refers to an active filter used only to reduce the current harmonics, while the second simulation uses an active filter that also acts on the reactive component of the current. For both simulations, two cases are considered. In one case, the output current of the LCL filter is used as the current feedback signal, while in the other case, the VSI current is used as the current feedback signal. The simulation results show the influence on the total current distortion as well as on the current ripple.
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Osnovni podaci: Voditelji:
Marko Koričić (Croatia), Željko Butković (Croatia)
Voditeljstvo:
Slavko Amon (Slovenia), Dubravko Babic (Croatia), Maurizio Ferrari (Italy), Mile Ivanda (Croatia), Tihomir Knežević (Croatia), Branimir Pejčinović (United States), Mirko Poljak (Croatia), Jörg Schulze (Germany), Tomislav Suligoj (Croatia), Aleksandar Szabo (Croatia), Davor Vinko (Croatia)
Prijava/Kotizacija:
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PRIJAVA / KOTIZACIJE
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CIJENA U EUR-ima
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Do 8.5.2023.
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Od 9.5.2023.
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| Članovi MIPRO i IEEE |
230
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260
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| Studenti (preddiplomski i diplomski studij) te nastavnici osnovnih i srednjih škola |
120
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140
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| Ostali |
250
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280
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Popust se ne odnosi na studente doktorskog studija.
Kontakt:
Marko Koričić
Fakultet elektrotehnike i računarstva
Unska 3
10000 Zagreb, Hrvatska
Tel.: +385 1 6129 671
GSM: +385 98 671 391
Fax: +385 1 6129 653
E-mail: marko.koricic@fer.hr
Najbolji radovi bit će nagrađeni.
Prihvaćeni radovi bit će objavljeni u zborniku radova s ISSN brojem. Prezentirani radovi na engleskom jeziku bit će poslani za uključenje u digitalnu bazu IEEE Xplore.
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Postoji mogućnost da se odabrani znanstveni radovi uz određenu doradu objave u sljedećim časopisima: Journal of Computing and Information Technology (CIT), MDPI Applied Science, MDPI Information Journal, Frontiers i EAI Endorsed Transaction on Scalable Information Systems.
Mjesto održavanja:
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